The record for the largest chip size sounds like something of a dubious proposition, but not in the case of TSMC. The company introduced chip-on-wafer-on-substrate (CoWoS) packaging technology, which will allow for the creation of system-in-package (SiP) systems that are several times larger than existing NVIDIA B200 or AMD Instinct MI300X processors. The processors will have monster dimensions of 120 x 120 mm and consume kilowatts of power.
«CoWoS®, SoIC and System-on-Wafer (TSMC-SoW™): TSMC’s chip-on-wafer (CoWoS) has been a key driver of the AI revolution, enabling customers to use more processor cores and high-bandwidth memory (HBM) stacked side-by-side on a single intermediate device. At the same time, our System on Integrated Circuits (SoIC) has established itself as the leading solution for 3D chip stacking, and customers are increasingly combining CoWoS with SoIC and other components to maximize system-on-package (SiP) integration
With System-on-Wafer, TSMC is offering a revolutionary new option that enables a large array of dies on a 300mm wafer, offering more processing power, taking up much less data center space and increasing performance per watt by orders of magnitude. TSMC’s first SoW offering, a wafer with a logic circuit based on Integrated Fan-Out (InFO) technology, is already in production. A chip-on-wafer version utilizing CoWoS technology is planned for 2027, enabling the integration of SoICs, HBMs, and other components to create a powerful system at the wafer level with computing power comparable to a data center server rack or even an entire server».
The platform utilizes the company’s previously developed InFO_SoW technology, which allows for the creation of large chips, as well as System on Integrated Chips (SoIC) technology. Another technology, Chip-on-Wafer (CoW), allows for the placement of memory or other elements on top of the system.
In fact, we are talking about processors comparable in size to a whole 300 mm silicon wafer, which will allow placing a huge number of cores. This method of packing cores will provide increased performance and energy efficiency through high speeds between components. Internally, the system will have low latency between cores and low resistance during power transfer. Unlike previous technologies, CoWoS allows for the use of different process technologies and high-speed HBM4 memory in the chip layout.
Sources: TSMC, Tom`s Hardware